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dual, 12-/14-/16-bit nano dacs ? with 5 ppm/c on-chip reference, i 2 c ? interface ad5627r/AD5647R/ad5667r, ad5627/ad5667 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features low power, smallest pin-compatible, dual nano dacs ad5627r/AD5647R/ad5667r 12-/14-/16-bit on-chip 1.25 v/2.5 v, 5 ppm/c reference ad5627/ad5667 12-/16-bit external reference only 3 mm x 3 mm lfcsp and 10-lead msop 2.7 v to 5.5 v power supply guaranteed monotonic by design power-on reset to zero scale per channel power-down hardware ldac and clr functions i 2 c-compatible serial interface supports standard (100 khz), fast (400 khz), and high speed (3.4 mhz) modes applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators functional block diagrams interface logic sda scl a ddr v dd gnd power-on reset 1.25v/2.5v ref v refin / v refout ad5627r/AD5647R/ad5667r power-down logic input register dac register string dac a v out a buffer input register dac register string dac b v out b ldac clr buffer 06342-001 figure 1. ad5627r/AD5647R/ad5667r interface logic sda scl a ddr v dd gnd power-on reset v refin ad5627/ad5667 power-down logic input register dac register string dac a v out a buffer input register dac register string dac b v out b ldac clr buffer 06342-002 figure 2. ad5627/ad5667 general description the ad5627r/AD5647R/ad5667r, ad5627/ad5667 members of the nano dac family are low power, dual, 12-, 14-, 16-bit buffered voltage-out dacs with/without on-chip reference. all devices operate from a single 2.7 v to 5.5 v supply, are guaranteed monotonic by design, and have an i 2 c- compatible serial interface. the ad5627r/AD5647R/ad5667r have an on-chip reference. the ad56x7rbcpz have a 1.25 v, 5 ppm/c reference, giving a full-scale output range of 2.5 v; the ad56x7rbrmz have a 2.5 v, 5 ppm/c reference, giving a full-scale output range of 5 v. the on-chip reference is off at power-up, allowing the use of an external reference. the internal reference is enabled via a software write. the ad5667 and ad5627 require an external reference voltage to set the output range of the dac. the ad56x7r/ad56x7 incorporate a power-on reset circuit that ensures the dac output powers up to 0 v, and remains there until a valid write takes place. the part contains a per- channel power-down feature that reduces the current consumption of the device to 480 na at 5 v and provides software-selectable output loads while in power-down mode. the low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. the on-chip precision output amplifier enables rail-to-rail output swing. the ad56x7r/ad56x7 use a 2-wire i 2 c-compatible serial interface that operates in stan dard (100 khz), fast (400 khz), and high speed (3.4 mhz) modes. table 1. related devices part no. description ad5663 2.7 v to 5.5 v, dual 16-bit dac, external reference, spi? interface ad5623r / ad5643r / ad5663r 2.7 v to 5.5 v, dual 12-, 14-, 16-bit dacs, internal reference, spi interface ad5625r / ad5645r / ad5665r , ad5625 / ad5665 2.7 v to 5.5 v, quad 12-, 14-, 16-bit dacs, with/without internal reference, i 2 c interface
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagrams............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 ac characteristics........................................................................ 5 i 2 c timing specifications............................................................ 6 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 typical performance characteristics ........................................... 10 terminology .................................................................................... 18 theory of operation ...................................................................... 20 d/a section................................................................................. 20 resistor string ............................................................................. 20 output amplifier........................................................................ 20 internal reference........................................................................ 20 external reference....................................................................... 20 serial interface ............................................................................ 21 write operation.......................................................................... 21 read operation........................................................................... 21 high speed mode....................................................................... 21 input shift register .................................................................... 23 multiple byte operation............................................................ 23 broadcast mode.......................................................................... 23 ldac function .......................................................................... 23 power-down modes .................................................................. 25 power-on reset and software reset ....................................... 26 clear pin ( clr ) .......................................................................... 26 internal reference setup (r versions) .................................... 26 application information................................................................ 27 using a reference as a power supply for the ad56x7r/ad56x7 ..................................................................... 27 bipolar operation using the ad56x7r/ad56x7 .................. 27 power supply bypassing and grounding................................ 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 29 revision history 1/07revision 0: initial version
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 3 of 32 specifications v dd = 2.7 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. table 2. parameter min typ max unit conditions/comments 1 static performance 2 ad5667r/ad5667 resolution 16 bits relative accuracy 8 12 lsb differential nonlinearity 1 lsb guaranteed monotonic by design AD5647R resolution 14 bits relative accuracy 2 4 lsb differential nonlinearity 0.5 lsb guaranteed monotonic by design ad5627r/ad5627 resolution 12 bits relative accuracy 0.5 1 lsb differential nonlinearity 0.25 lsb guaranteed monotonic by design zero-code error 2 10 mv all 0s loaded to dac register offset error 1 10 mv full-scale error ?0.1 1 % of fsr all 1s loaded to dac register gain error 1.5 % of fsr zero-code error drift 2 v/c gain temperature coefficient 2.5 ppm of fsr/c dc power supply rejection ratio ?100 db dac code = midscale ; v dd = 5 v 10% dc crosstalk (external reference) 15 v due to full-scale output change, r l = 2 k to gnd or 2 k to v dd 10 v/ma due to load current change 8 v due to powering down (per channel) dc crosstalk (internal reference) 25 v due to full-scale output change, r l = 2 k to gnd or 2 k to v dd 20 v/ma due to load current change 10 v due to powering down (per channel) output characteristics 3 output voltage range 0 v dd v capacitive load stability 2 nf r l = 10 nf r l = 2 k dc output impedance 0.5 short-circuit current 30 ma v dd = 5 v power-up time 4 s coming out of power-down mode; v dd = 5 v reference inputs reference current 110 130 a v ref = v dd = 5.5 v reference input range 0.75 v dd v reference input impedance 50 k reference output (lfcsp_wd package) output voltage 1.247 1.253 v at ambient reference tc 3 10 ppm/c output impedance 7.5 k reference output (msop package) output voltage 2.495 2.505 v at ambient reference tc 3 5 10 ppm/c output impedance 7.5 k
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 4 of 32 parameter min typ max unit conditions/comments 1 logic inputs (addr, clr , ldac ) 3 i in , input current 1 a v inl , input low voltage 0.15 v dd v v inh , input high voltage 0.85 v dd v c in , pin capacitance 2 pf addr 20 pf clr , ldac v hyst , input hysteresis 0.1 v dd v logic inputs (sda, scl) i in , input current 1 a v inl , input low voltage 0.3 v dd v v inh , input high voltage 0.7 v dd v c in , pin capacitance 2 pf v hyst , input hysteresis 0.1 v dd v logic outputs (open-drain) v ol , output low voltage 0.4 v i sink = 3 ma 0.6 v i sink = 6 ma floating-state leakage current 1 a floating-state output capacitance 2 pf power requirements v dd 2.7 5.5 v i dd (normal mode) 4 v ih = v dd , v il = gnd v dd = 4.5 v to 5.5 v 0.4 0.5 ma internal reference off v dd = 2.7 v to 3.6 v 0.35 0.45 ma internal reference off v dd = 4.5 v to 5.5 v 0.95 1.15 ma internal reference on v dd = 2.7 v to 3.6 v 0.8 0.95 ma internal reference on i dd (all power-down modes) 5 0.48 1 a v ih = v dd , v il = gnd 1 temperature range: b grade: ?40c to +105c. 2 linearity calculated using a reduced code range: ad 5567r/ad5667 (code 512 to code 65,024); AD5647R (code 128 to code 16,256); ad5627r/ad5627 (code 32 to code 4064). output unloaded. 3 guaranteed by design and characterization, not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all dacs powered down.
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 5 of 32 ac characteristics v dd = 2.7 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. 1 table 3. parameter 2 min typ max unit conditions/comments 3 output voltage settling time ad5627r/ad5627 3 4.5 s ? to ? scale settling to 0.5 lsb AD5647R 3.5 5 s ? to ? scale settling to 0.5 lsb ad5667r/ad5667 4 7 s ? to ? scale settling to 2 lsb slew rate 1.8 v/s digital-to-analog glitch impulse 15 nv-s 1 lsb change around major carry transition digital feedthrough 0.1 nv-s reference feedthrough ?90 db v ref = 2 v 0.1 v p-p, frequency 10 hz to 20 mhz digital crosstalk 0.1 nv-s analog crosstalk 1 nv-s external reference 4 nv-s internal reference dac-to-dac crosstalk 1 nv-s external reference 4 nv-s internal reference multiplying bandwidth 340 khz v ref = 2 v 0.1 v p-p total harmonic distortion ?80 db v ref = 2 v 0.1 v p-p, frequency = 10 khz output noise spectral density 120 nv/hz dac code = midscale, 1 khz 100 nv/hz dac code = midscale, 10 khz output noise 15 v p-p 0.1 hz to 10 hz 1 guaranteed by design and characterization, not production tested. 2 see the terminology section. 3 temperature range is ?40c to +105c, typical @ 25c.
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 6 of 32 i 2 c timing specifications v dd = 2.7 v to 5.5 v; all specifications t min to t max , f scl = 3.4 mhz, unless otherwise noted. 1 table 4. parameter conditions 2 min max unit description f scl 3 standard mode 100 khz serial clock frequency fast mode 400 khz high speed mode, c b = 100 pf 3.4 mhz high speed mode, c b = 400 pf 1.7 mhz t 1 standard mode 4 s t high , scl high time fast mode 0.6 s high speed mode, c b = 100 pf 60 ns high speed mode, c b = 400 pf 120 ns t 2 standard mode 4.7 s t low , scl low time fast mode 1.3 s high speed mode, c b = 100 pf 160 ns high speed mode, c b = 400 pf 320 ns t 3 standard mode 250 ns t su;dat , data setup time fast mode 100 ns high speed mode 10 ns t 4 standard mode 0 3.45 s t hd;dat , data hold time fast mode 0 0.9 s high speed mode, c b = 100 pf 0 70 ns high speed mode, c b = 400 pf 0 150 ns t 5 standard mode 4.7 s t su;sta, setup time for a repeated start condition fast mode 0.6 s high speed mode 160 ns t 6 standard mode 4 s t hd;sta , hold time (repeated) start condition fast mode 0.6 s high speed mode 160 ns t 7 standard mode 4.7 s t buf , bus free time between a stop and a start condition fast mode 1.3 s t 8 standard mode 4 s t su;sto , setup time for a stop condition fast mode 0.6 s high speed mode 160 ns t 9 standard mode 1000 ns t rda , rise time of sda signal fast mode 300 ns high speed mode, c b = 100 pf 10 80 ns high speed mode, c b = 400 pf 20 160 ns t 10 standard mode 300 ns t fda , fall time of sda signal fast mode 300 ns high speed mode, c b = 100 pf 10 80 ns high speed mode, c b = 400 pf 20 160 ns t 11 standard mode 1000 ns t rcl , rise time of scl signal fast mode 300 ns high speed mode, c b = 100 pf 10 40 ns high speed mode, c b = 400 pf 20 80 ns t 11a standard mode 1000 ns t rcl1 , rise time of scl signal after a repeated start condition and after an acknowledge bit fast mode 300 ns high speed mode, c b = 100 pf 10 80 ns high speed mode, c b = 400 pf 20 160 ns
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 7 of 32 parameter conditions 2 min max unit description t 12 standard mode 300 ns t fcl , fall time of scl signal fast mode 300 ns high speed mode, c b = 100 pf 10 40 ns high speed mode, c b = 400 pf 20 80 ns t 13 standard mode 10 ns ldac pulse width low fast mode 10 ns high speed mode 10 ns t 14 standard mode 300 ns falling edge of 9 th scl clock pulse of last byte of valid write to ldac falling edge fast mode 300 ns high speed mode 30 ns t 15 standard mode 20 ns clr pulse width low fast mode 20 ns high speed mode 20 ns t sp 4 fast mode 0 50 ns pulse width of spike suppressed high speed mode 0 10 ns 1 see figure 3 . high speed mode timing specification a pplies only to the ad5627rbrmz-2/ad5627brmz-2reel7 and ad5667rbrmz-2/ad5667brmz-2reel7. 2 cb refers to the capacitance on the bus line. 3 the sda and scl timing is measured with the input filters enable d. switching off the input filt ers improves the transfer rate but has a negative effect on emc behavior of the part. 4 input filtering on the scl and sda inputs suppresses noise spikes that are less than 50 ns for fast mode or 10 ns for high spe ed mode. scl sda ps s p t 8 t 6 t 5 t 3 t 10 t 9 t 4 t 6 t 1 t 2 t 11 t 12 t 14 clr t 13 t 15 ldac* t 7 *asynchronous ldac update mode. 06342-003 figure 3. 2-wire serial interface timing diagram
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 8 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v v out to gnd ?0.3 v to v dd + 0.3 v v refin /v refout to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v operating temperature range, industrial ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j maximum) 150c power dissipation (t j max ? t a )/ ja ja thermal impedance lfcsp_wd package (4-layer board) 61c/w msop package 150.4c/w reflow soldering peak temperature, pb-free 260c 5c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 9 of 32 pin configuration and fu nction descriptions 1 v out a 10 v refin 2 v out b 9 v dd 3 gnd 8 sda 4 ldac 7 scl 5 clr 6 addr ad5627/ ad5667 top view (not to scale) exposed pad tied to gnd on lfcsp package. 06342-101 figure 4. ad5627/ad5667 pin configuration 1 v out a 10 v refin /v refout 2 v out b 9 v dd 3 gnd 8 sda 4 ldac 7 scl 5 clr 6 addr ad5627r/ AD5647R/ ad5667r top view (not to scale) exposed pad tied to gnd on lfcsp package. 06342-102 figure 5. ad5627r/AD5647R/ad5667r pin configuration table 6. pin function descriptions pin no. mnemonic description 1 v out a analog output voltage from dac a. the o utput amplifier has rail-to-rail operation. 2 v out b analog output voltage from dac b. the o utput amplifier has rail-to-rail operation. 3 gnd ground reference point for all circuitry on the part. 4 ldac pulsing this pin low allows any or all dac registers to be updated if the inputs have new data. this allows simultaneous updates of all dac outputs. alternat ively, this pin can be tied permanently low. 5 clr asynchronous cl ear input. the clr input is falling-edge sensitive. while clr is low, all ldac pulses are ignored. when clr is activated, zero scale is loaded to all input and dac registers. this clears the output to 0 v. the part exits clear code mode on the falling edge of the 9 th clock pulse of the last byte of valid write. if clr is activated during a write sequence, the write is aborted. if clr is activated during high speed mode the part will exit high speed mode. 6 addr three-state address input. sets the two least significant bits (bit a1, bit a0) of the 7-bit slave address. 7 scl serial clock line. this is used in co njunction with the sda line to clock data into or out of the 24-bit input register. 8 sda serial data line. this is used in conjunction with the scl line to clock da ta into or out of the 24-bit input register. it is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. 9 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 10 v refin /v refout the ad56x7r have a common pin for reference input and refere nce output. when using the in ternal reference, this is the reference output pin. when using an ex ternal reference, this is the reference input pin. the default for this pin is as a reference input. (the internal reference and reference output are only available on r suffix versions.) the ad56x7 has a reference input pin only.
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 10 of 32 typical performance characteristics code inl error (lsb) 10 4 6 8 0 2 ?6 ?10 ?8 ?2 ?4 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k v dd = v ref = 5v t a = 25c 06342-005 figure 6. ad5667 inl, external reference code inl error (lsb) 4 ?4 0 2500 5000 7500 10000 12500 15000 ?3 ?2 ?1 0 1 2 3 v dd = v ref = 5v t a = 25c 06342-006 figure 7. AD5647R inl, external reference code inl error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 ?0.8 ?0.6 ?0.4 0 0.4 0.2 ?0.2 0.6 0.8 v dd = v ref = 5v t a = 25c 06342-100 figure 8. ad5627 inl, external reference code dnl error (lsb) 1.0 0.6 0.4 0.2 0.8 0 ?0.4 ?0.2 ?0.6 ?1.0 ?0.8 0 10k 20k 30k 40k 50k 60k v dd = v ref = 5v t a = 25c 0 6342-007 figure 9. ad5667 dnl, external reference dnl error (lsb) 0.5 0.3 0.2 0.1 0.4 0 ?0.2 ?0.1 ?0.3 ?0.5 ?0.4 v dd = v ref = 5v t a = 25c code 0 2500 5000 7500 10000 12500 15000 0 6342-008 figure 10. dnl AD5647R, external reference dnl error (lsb) 0.20 0.10 0.05 0.15 0 ?0.05 ?0.10 ?0.20 ?0.15 code 0 500 1000 1500 2000 2500 3000 3500 4000 v dd = v ref = 5v t a = 25c 0 6342-009 figure 11. ad5627 dnl, external reference
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 11 of 32 code inl error (lsb) 10 8 0 ?10 ?6 ?8 ?4 6 ?2 4 2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 5v v refout = 2.5v t a = 25c 06342-010 figure 12. ad5667r inl, 2.5 v internal reference code inl error (lsb) 4 3 ?4 ?3 ?2 2 ?1 1 0 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 v dd =5v v refout =2.5v t a =25c 06342-011 figure 13. AD5647R inl, 2.5 v internal reference code inl error (lsb) 1.0 0.8 0 ?1.0 ?0.8 ?0.6 0.6 ?0.4 ?0.2 0.4 0.2 0 1000 500 2000 1500 3500 3000 2500 4000 v dd =5v v refout =2.5v t a = 25c 06342-012 figure 14. ad5627r inl, 2.5 v internal reference code dnl error (lsb) 1.0 0.8 0 ?1.0 ?0.6 ?0.8 ?0.4 0.6 ?0.2 0.4 0.2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd =5v v refout =2.5v t a =25c 06342-013 figure 15. ad5667r dnl, 2.5 v internal reference code dnl error (lsb) 0.5 0.4 0 ?0.5 ?0.3 ?0.4 ?0.2 0.3 ?0.1 0.2 0.1 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 v dd = 5v v refout = 2.5v t a = 25c 0 6342-014 figure 16. AD5647R dnl, 2.5 v internal reference code dnl error (lsb) 0.20 0.15 0 ?0.20 ?0.15 ?0.10 0.10 ?0.05 0.05 0 1000 500 2000 1500 3500 3000 2500 4000 v dd = 5v v refout = 2.5v t a = 25c 0 6342-015 figure 17. ad5627r dnl, 2.5 v internal reference
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 12 of 32 code inl error (lsb) 10 8 4 6 2 0 ?4 ?2 ?6 ?8 ?10 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 3v v refout = 1.25v t a = 25c 06342-016 figure 18. ad5667r inl,1.25 v internal reference code inl error (lsb) 4 ?4 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 3 2 1 0 ?1 ?2 ?3 v dd = 3v v refout = 1.25v t a = 25c 06342-017 figure 19. AD5647R inl, 1.25 v internal reference code inl error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 v dd = 3v v refout = 1.25v t a = 25c 06342-018 figure 20. ad5627r inl,1.25 v internal reference code dnl error (lsb) 1.0 0.8 0.4 0.6 0.2 0 ?0.4 ?0.2 ?0.6 ?0.8 ?1.0 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 3v v refout = 1.25v t a = 25c 06342-019 figure 21. ad5667r dnl,1.25 v internal reference code dnl error (lsb) 0.5 ?0.5 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 0 0.4 0.3 0.2 0.1 ?0.1 ?0.2 ?0.3 ?0.4 v dd = 3v v refout = 1.25v t a = 25c 06342-020 figure 22. AD5647R dnl,1.25 v internal reference code dnl error (lsb) 0.20 ?0.20 0 500 1000 1500 2000 2500 3000 3500 4000 0 0.15 0.10 0.05 ?0.05 ?0.10 ?0.15 v dd = 3v v refout = 1.25v t a = 25c 06342-021 figure 23. ad5627r dnl, 1.25 v internal reference
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 13 of 32 temperature (c) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 ?40 ?20 40 20 01 80 60 0 0 min dnl max dnl max inl min inl v dd = v ref = 5v 06342-022 figure 24. inl error and dnl error vs. temperature v ref (v) error (lsb) 10 4 6 8 2 0 ?8 ?6 ?4 ?2 ?10 0.75 1.25 1.75 2.25 4.25 3.75 3.25 2.75 4.75 min dnl max dnl max inl min inl v dd = 5v t a = 25c 06342-023 figure 25. inl and dnl error vs. v ref v dd (v) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 2.7 3.2 3.7 4.7 4.2 5.2 min dnl max dnl max inl min inl t a = 25c 06342-024 figure 26. inl and dnl error vs. supply temperature (c) error (% fsr) 0 ?0.04 ?0.02 ?0.06 ?0.08 ?0.10 ?0.18 ?0.16 ?0.14 ?0.12 ?0.20 ?40 ?20 40 200 100 80 60 v dd = 5v gain error full-scale error 06342-025 figure 27. gain error and full-scale error vs. temperature temperature (c) error (mv) 1.5 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 ?40 ?20 40 20 08 60 100 0 offset error zero-scale error 06342-026 figure 28. zero-scale error and offset error vs. temperature v dd (v) error (% fsr) 1.0 ?1.5 ?1.0 ?0.5 0 0.5 ?2.0 2.7 3.2 3.7 4.7 4.2 5.2 gain error full-scale error 06342-027 figure 29. gain error and full-scale error vs. supply
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 14 of 32 v dd (v) error (mv) 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 2.7 3.2 4.2 3.7 5.2 4.7 zero-scale error offset error t a = 25c 06342-028 figure 30. zero-scale error and offset error vs. supply i dd (ma) number of devices 0 1 8 1 6 1 4 1 2 1 0 8 6 4 2 0.44 0.42 0.40 0.38 0.36 0.34 0.32 0.30 v dd = 3.6v v dd = 5.5v 06342-029 figure 31. i dd histogram with external reference i dd (ma) number of devices 0 1 4 1 2 1 0 8 6 4 2 0.74 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 v dd = 3.6v v dd = 5.5v 06342-030 v refout = 2.5v v refout = 1.25v figure 32. i dd histogram with internal reference current (ma) error vol t age (v) 0.5 0.4 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 ?10 ?8 ?6 ?4 ?2 0 2 4 8 61 0 v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v dac loaded with zero-scale sinking current dac loaded with full-scale sourcing current 0 6342-031 figure 33. headroom at rails vs. source and sink current (ma) v out (v) 6 5 4 3 2 1 ?1 0 ?30 ?20 ?10 0 10 20 30 v dd = 5v v refout = 2.5v t a = 25c zero scale full scale midscale 1/4 scale 3/4 scale 0 6342-046 figure 34. ad56x7r with 2.5 v reference, source and sink capability current (ma) v out (v) 4 ?1 0 1 2 3 ?30 ?20 ?10 0 10 20 30 v dd = 3v v refout = 1.25v t a = 25c zero scale full scale midscale 1/4 scale 3/4 scale 0 6342-047 figure 35. ad56x7r with 1.25 v reference, source and sink capability
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 15 of 32 code i dd (ma) 0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 512 10512 20512 30512 40512 50512 60512 t a = 25c v dd = 5v, v refout = 2.5v v dd = v ref = 5v 0 6342-060 figure 36. supply current vs. code supply voltage (v) i dd (ma) 0 0.05 0.10 0.15 0.25 0.20 0.30 0.40 0.35 3.2 2.7 3.7 4.2 4.7 5.2 t a = 25c 06342-061 figure 37. supply current vs. supply voltage temperature (c) i dd (ma) 0.45 0.05 0.10 0.15 0.20 0.35 0.40 0.25 0.30 0 ?40 ?20 0 20 40 60 80 100 06342-063 v dd = v refin = 5v v dd = v refin = 3v figure 38. supply current vs. temperature time base = 4s/div v dd = v ref = 5v t a = 25c full-scale code change 0x0000 to 0xffff output loaded with 2k ? and 200pf to gnd v out = 909mv/div 1 06342-048 figure 39. full-scale settling time, 5 v ch1 2.0v ch2 500mv m100s 125ms/s a ch1 1.28v 8.0ns/pt v dd = v ref = 5v t a = 25c v out v dd 1 2 max(c2) 420.0mv 06342-049 figure 40. power-on reset to 0 v v dd = 5v sync slck v out 1 3 ch1 5.0v ch3 5.0v ch2 500mv m400ns a ch1 1.4v 2 0 6342-050 figure 41. exiting po wer-down to midscale
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 16 of 32 sample number v out (v) 2.521 2.522 2.523 2.524 2.525 2.526 2.527 2.528 2.529 2.530 2.531 2.532 2.533 2.534 2.535 2.536 2.537 2.538 0 50 100 150 350 400 200 250 300 450 512 v dd = v ref = 5v t a = 25c 5ns/sample number glitch impulse = 9.494nv 1lsb change around midscale (0x8000 to 0x7fff) 0 6342-058 figure 42. digital-to-analog glitch impulse (negative) sample number v out (v) 2.491 2.492 2.493 2.494 2.495 2.496 2.497 2.498 0 50 100 150 350 400 200 250 300 450 512 v dd = v ref = 5v t a = 25c 5ns/sample number analog crosstalk = 0.424nv 0 6342-059 figure 43. analog crosstalk, external reference sample number v out (v) 2.456 2.458 2.460 2.462 2.464 2.466 2.468 2.470 2.472 2.474 2.476 2.478 2.480 2.482 2.484 2.486 2.488 2.490 2.492 2.494 2.496 0 50 100 150 350 400 200 250 300 450 512 v dd = 5v v refout = 2.5v t a = 25c 5ns/sample number analog crosstalk = 4.462nv 0 6342-062 figure 44. analog crosstalk, internal reference 1 v dd = v ref = 5v t a = 25c dac loaded with midscale 4s/div 2v/di v 06342-051 figure 45. 0.1 hz to 10 hz output noise plot, external reference 5s/div 10v/di v 1 v dd = 5v v refout = 2.5v t a = 25c dac loaded with midscale 06342-052 figure 46. 0.1 hz to 10 hz output noise plot, 2.5 v internal reference 4s/div 5v/di v 1 v dd = 3v v refout = 1.25v t a = 25c dac loaded with midscale 06342-053 figure 47. 0.1 hz to 10 hz output noise plot,1.25 v internal reference
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 17 of 32 frequency (hz) output noise (nv/ hz) 800 0 100 200 300 400 500 600 700 100 10k 1k 100k 1m v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v t a = 25c midscale loaded 0 6342-054 figure 48. noise spectral density, internal reference frequency (hz) (db) ? 20 ?50 ?80 ?30 ?40 ?60 ?70 ?90 ?100 2k 4k 6k 8k 10k v dd = 5v t a = 25c dac loaded with full scale v ref = 2v 0.3v p-p 0 6342-055 figure 49. total harmonic distortion capacitance (nf) time (s) 16 14 12 10 8 6 4 012 34567 9 81 0 v ref = v dd t a = 25c v dd = 5v v dd = 3v 0 6342-056 figure 50. settling time vs. capacitive load frequency (hz) (db) 5 ?40 10k 100k 1m 10m ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 v dd = 5v t a = 25c 06342-057 figure 51. multiplying bandwidth
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 18 of 32 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. zero-code error zero-code error is a measurement of the output error when zero scale (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the ad5667r because the output of the dac cannot go below 0 v due to a combination of the offset errors in the dac and the output amplifier. zero-code error is expressed in mv. full-scale error full-scale error is a measurement of the output error when full- scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed in % of full-scale range (fsr). gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal expressed in % of fsr. zero-code error drift zero-code error drift is a measurement of the change in zero- code error with a change in temperature. it is expressed in v/c. gain temperature coefficient gain temperature coefficient is a measurement of the change in gain error with changes in temperature. it is expressed in ppm of fsr/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the ad5667r with code 512 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) dc psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in db. v ref is held at 2 v and v dd is varied by 10%. output voltage settling time output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full-scale input change and is measured from the rising edge of the stop condition. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s, and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000) (see figure 42 ). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-s, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in db. output noise spectral density output noise spectral density is a measurement of the internally generated random noise. random noise is characterized as a spectral density. it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nv/hz. a plot of noise spectral density can be seen in figure 48 . dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac (or soft power-down and power-up) while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in v/ma. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv-s.
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 19 of 32 analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa), then executing a software ldac and monitoring the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv-s. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent analog output change of another dac. it is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa) with ldac low while monitoring the output of the victim channel that is at midscale. the energy of the glitch is expressed in nv-s. multiplying bandwidth the multiplying bandwidth is a measure of the finite bandwidth of the amplifiers within the dac. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) thd is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in db.
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 20 of 32 theory of operation d/a section the ad56x7r/ad56x7 dacs are fabricated on a cmos process. the architecture consists of a string dac followed by an output buffer amplifier. figure 52 shows a block diagram of the dac architecture. dac register resistor string ref (+) v dd gnd ref (?) v out output amplifier gain = +2 06342-032 figure 52. dac architecture because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n refin out d vv 2 the ideal output voltage when using the internal reference is given by ? ? ? ? ? ? = n refout out d vv 2 2 where: d is the decimal equivalent of the binary code that is loaded to the dac register: 0 to 4095 for ad5627r/ad5627 (12-bit). 0 to 16,383 for AD5647R (14-bit). 0 to 65,535 for ad5667r/ad5667 (16-bit). n is the dac resolution. resistor string the resistor string is shown in figure 53 . it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. output amplifier the output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . it can drive a load of 2 k in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 33 and figure 34 . the slew rate is 1.8 v/s with a ? to ? full-scale settling time of 7 s. r r r r r to output amplifier 0 6342-033 figure 53. resistor string internal reference the ad5627r/AD5647R/ad5667r feature an on-chip reference. versions without the r suffix require an external reference. the on-chip reference is off at power-up and is enabled via a write to a control register. see the internal reference setup section for details. versions packaged in a 10-lead lfcsp package have a 1.25 v reference, giving a full-scale output of 2.5 v. these parts can be operated with a v dd supply of 2.7 v to 5.5 v. versions packaged in a 10-lead msop package have a 2.5 v reference, giving a full- scale output of 5 v. the parts are functional with a v dd supply of 2.7 v to 5.5 v, but with a v dd supply of less than 5 v, the output is clamped to v dd . see the ordering guide for a full list of models. the internal reference associated with each part is available at the v refout pin. a buffer is required if the reference output is used to drive external loads. when using the internal reference, it is recommended that a 100 nf capacitor be placed between the reference output and gnd for reference stability. external reference the ad5627/ad5667 require an external reference, which is applied at the v refin pin. the v refin pin on the ad56x7r allows the use of an external reference if the application requires it. the default condition of the on-chip reference is off at power- up. all devices can be operated from a single 2.7 v to 5.5 v supply.
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 21 of 32 serial interface the ad56x7r/ad56x7 have 2-wire i 2 c-compatible serial interfaces (refer to i 2 c-bus specification , version 2.1, january 2000, available from philips semiconductor). the ad56x7r/ad56x7 can be connected to an i 2 c bus as a slave device, under the control of a master device. see figure 3 for a timing diagram of a typical write sequence. the ad56x7r/ad56x7 support standard (100 khz), fast (400 khz), and high speed (3.4 mhz) data transfer modes. high speed operation is only available on select models. see the ordering guide for a full list of models. support is not provided for 10-bit addressing and general call addressing. the ad56x7r/ad56x7 each have a 7-bit slave address. the five msbs are 00011 and the two lsbs (a1, a0) are set by the state of the addr address pin. the facility to make hardwired changes to addr allows the user to incorporate up to three of these devices on one bus, as outlined in table 7 . table 7. device address selection addr pin connection a1 a0 v dd 0 0 no connection 1 0 gnd 1 1 the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7-bit slave address. the slave address corresponding to the transmitted address responds by pulling sda low during the 9 th clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the 9 th clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10 th clock pulse, and then high during the 10 th clock pulse to establish a stop condition. write operation when writing to the ad56x7r/a d56x7, the user must begin with a start command followed by an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. th e ad56x7r/ad56x7 requires two bytes of data for the dac and a command byte that controls various dac functions. three byte s of data must therefore be written to the dac, the comma nd byte followed by the most significant data byte and the le ast significant data byte, as shown in figure 54 . all these data bytes are acknowledged by the ad56x7r/ad56x7. a stop condition follows. read operation when reading data back from the ad56x7r/ad56x7, the user begins with a start command followed by an address byte (r/ w = 1), after which the dac acknowledges that it is prepared to transmit data by pulling sda low. three bytes of data are then read from the dac, which are acknowledged by the master, as shown in figure 55 . a stop condition follows. high speed mode the ad5627rbrmz and the ad5667rbrmz offer high speed serial communication with a clock frequency of 3.4 mhz. see the ordering guide for details. high speed mode communication commences after the master addresses all devices connected to the bus with the master code 00001xxx to indicate that a high speed mode transfer is to begin (see figure 56 ). no device connected to the bus is permitted to acknowledge the high speed master code. therefore, the code is followed by a no acknowledge. the master must then issue a repeated start followed by the device address. the selected device then acknowledges its address. all devices continue to operate in high speed mode until the master issues a stop condition. when the stop condition is issued, the devices return to standard/fast mode. the part also returns to standard/fast mode when clr is activated while the part is in high speed mode.
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 22 of 32 frame 2 command byte frame 1 slave address 19 9 1 scl start by master ack. by ad56x7 ack. by ad56x7 sda r/w db23 a0a1 1 00 0 1 db22 db21 db20 db19 db18 db17 db16 19 1 ack. by ad56x7 ack. by ad56x7 frame 4 least significant data byte frame 3 most significant data byte 9 stop by master scl ( continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 06342-103 figure 54. i 2 c write operation frame 2 command byte frame 1 slave address 19 9 1 scl start by master ack. by ad56x7 ack. by master sda r/w db23 a0a1 1 00 0 1 db22 db21 db20 db19 db18 db17 db16 19 1 ack. by master no ack. frame 4 least significant data byte frame 3 most significant data byte 9 stop by master scl ( continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 6342-104 figure 55. i 2 c read operation scl 0 0 0 0 1 x x x 0 0 0 1 1 a1 a0 r/w sda 19 19 no ack sr start by master ack. by ad56x7 hs-mode master code serial bus address byte fast mode high-speed mode 06342-105 figure 56. placing the ad5627rbrmz-2/ad5667rbrmz-2 in high speed mode
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 23 of 32 input shift register the input shift register is 24 bits wide. data is loaded into the device as a 24-bit word under the control of a serial clock input, scl. the timing diagram for this operation is shown in figure 3 . the 8 msbs make up the command byte. db23 is reserved and should always be set to 0 when writing to the device. db22 (s) is used to select multiple byte operation the next three bits are the command bits (c2, c1, c0) that control the mode of operation of the device. see table 8 for details. the last 3 bits of first byte are the address bits (a2, a1, a0). see table 9 for details. the rest of the bits are the 16-, 14-, 12-bit data word. the data word comprises the 16-, 14-, 12-bit input code followed by two or four dont cares for the AD5647R and the ad 5627r/ad5627, respectively (see figure 59 through figure 61 ). multiple byte operation multiple byte operation is su pported on the ad56x7r/ad56x7. a 2-byte operation is useful for applications that require fast dac updating and do not need to change the command byte. the s bit (db22) in the command register can be set to 1 for 2- byte mode of operation (see figure 57 ). for standard 3-byte and 4-byte operation, the s bit (db22) in the command byte should be set to 0 (see figure 58 ). broadcast mode broadcast addressing is supported on the ad56x7r/ad56x7. broadcast addressing can be used to synchronously update or power down multiple ad56x7r /ad56x7 devices. using the broadcast address, the ad56x7r/ad56x7 responds regardless of the states of the address pins. broadcast is supported only in write mode. the ad56x7r/ad56x7 broadcast address is 00010000. table 8. command definition c2 c1 c0 command 0 0 0 write to input register n 0 0 1 update dac register n 0 1 0 write to input register n , update all (software ldac ) 0 1 1 write to and update dac channel n 1 0 0 power up/power down 1 0 1 reset 1 1 0 ldac register setup 1 1 1 internal reference setup (on/off ) table 9. dac address command a2 a1 a0 address ( n ) 0 0 0 dac a 0 0 1 dac b 1 1 1 both dacs ldac function the ad56x7r/ad56x7 dacs have double-buffered interfaces consisting of two banks of regi sters, input registers and dac registers. the input registers are connected directly to the input shift register, and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac registers contain the digital codes used by the resistor strings. access to the dac registers is controlled by the ldac pin. when the ldac pin is high, the dac registers are latched and the input registers can change state without affecting the contents of the dac registers. when ldac is brought low, however, the dac registers become transparent and the contents of the input registers are transferred to them. the double- buffered interface is useful if the user requires simultaneous updating of all dac outputs. the user can write to one of the input registers individually and then, by bringing ldac low when writing to the other dac input register, all outputs update simultaneously. these parts each contain an extra feature whereby a dac register is not updated unless its input register has been updated since the last time ldac was brought low. normally, when ldac is brought low, the dac registers ar e filled with the contents of the input registers. in the case of the ad56x7r/ad56x7, the dac register updates only if the input register has changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. the outputs of all dacs can be simultaneously updated, using the hardware ldac pin.
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 24 of 32 slave address command byte most significant data byte most significant data byte least significant data byte least significant data byte s = 1 block 1 s = 1 block 2 most significant data byte least significant data byte stop s = 1 block n 06342-106 figure 57. multiple block write with initial command byte only (s = 1) slave address command byte most significant data byte command byte least significant data byte most significant data byte least significant data byte s = 0 block 1 s = 0 block 2 most significant data byte command byte least significant data byte stop s = 0 block n 06342-107 figure 58. multiple block write with command byte in each block (s = 0) db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r s reserved byte selection c2 c1 c0 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command dac address dac data dac data command byte data high byte data low byte 06342-108 figure 59. ad5667r/ad5667 input shift register (16-bit dac) db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r s reserved byte selection c2 c1 c0 a2 a1 a0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x command dac address dac data dac data command byte data high byte data low byte 06342-109 figure 60. AD5647R input shift register (14-bit dac) db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r s reserved byte selection c2 c1 c0 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x command dac address dac data dac data command byte data high byte data low byte 06342-110 figure 61. ad5627r/ad5627 input shift register (12-bit dac)
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 25 of 32 synchronous ldac the dac registers are updated after new data is read in. ldac can be permanently low or pulsed. asynchronous ldac the outputs are not updated at the same time that the input registers are written to. when ldac goes low, the dac registers are updated with the contents of the input register. the ldac register gives the user full flexibility and control over the hardware ldac pin. this register allows the user to select which combination of channels to simultaneously update when the hardware ldac pin is executed. setting the ldac bit register to 0 for a dac channel means that the update of this channel is controlled by the ldac pin. if this bit is set to 1, this channel synchronously updates, that is, the dac register is updated after new data is read in, regardless of the state of the ldac pin. it effectively sees the ldac pin as being pulled low. see table 10 for the ldac register mode of operation. this flexibility is useful in applications when the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. writing to the dac using command 110 loads the 2-bit ldac register [db1:db0]. the default for each channel is 0, that is, the ldac pin works normally. setting the bits to 1 means the dac register is updated, regardless of the state of the ldac pin. see figure 63 for contents of the input shift register during the ldac register setup command. table 10. ldac register mode of operation: load dac register ldac bits (db1 to db0) ldac pin ldac operation 0 1/0 determined by ldac pin. 1 x = dont care the dac registers are updated after new data is read in. power-down modes command 100 is reserved for the power-up/down function. the power-up/down modes are programmed by setting bit db5 and bit db4. this defines the output state of the dac amplifier, as shown in tabl e 11 . bit db1and bit db0 determine to which dac or dacs the power-up/down command is applied. setting one of these bits to 1 applies the power-up/down state defined by db5 and db4 to the corresponding dac. if a bit is 0, the state of the dac is unchanged. figure 65 shows the contents of the input shift register for the power up/down command. when bit db5 and bit db4 are set to 0, the part works normally with its normal power consumption of 400 a at 5 v. however, for the three power-down modes, the supply current falls to 480 na at 5 v. not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this allows the output impedance of the part to be known while the part is in power-down mode. the outputs can either be connected internally to gnd through a 1 k or 100 k resistor, or left open-circuited (three-state) as shown in figure 62 . table 11. modes of operation for the ad56x7r/ad56x7 db5 db4 operating mode 0 0 normal operation power-down modes 0 1 1 k pull-down to gnd 1 0 100 k pull-down to gnd 1 1 three-state, high impedance resistor network v out resistor string dac power-down circuitry amplifier 06342-038 figure 62. output stage during power-down the bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shut down when power- down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 4 s for v dd = 5 v. r s c2 c1 c0 a2 a1 a0 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 x reserved don?t care 1 1 0 a2 a1 a0 x x x x x x x x x x x x x x dacb daca command dac address (don?t care) don?t care don?t care dac select (0 = ldac pin enabled) 06342-111 figure 63. ldac setup command
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 26 of 32 power-on reset and software reset the ad56x7r/ad56x7 contain a power-on reset circuit that controls the output voltage during power-up. the device powers up to 0 v and the output remains powered up at this level until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. any events on ldac or clr during power-on reset are ignored. there is also a software reset function. command 101 is the software reset command. the software reset command contains two reset modes that are software programmable by setting bit db0 in the input shift register. table 12 shows how the state of the bit corresponds to the software reset modes of operation of the devices. figure 64 shows the contents of the input shift register during the software reset mode of operation. table 12. software reset modes for the ad56x7r/ad56x7 db0 registers reset to zero 0 dac register input shift register 1 (power-on reset) dac register input shift register ldac register power-down register internal reference setup register clear pin (clr ) the ad56x7r/ad56x7 has an asynchronous clear input. the clr input is falling-edge sensitive. while clr is low, all ldac pulses are ignored. when clr is activated, zero scale is loaded to all input and dac registers. this clears the output to 0 v. the part exits clear code mode on the on the falling edge of the 9 th clock pulse of the last byte of valid write. if clr is activated during a write sequence, the write is aborted. if clr is activated during high speed mode, the part exits high speed mode to standard/fast mode. internal reference setup (r versions) the on-chip reference is off at power-up by default. it can be turned on by sending the reference setup command (111) and setting db0 in the input shift register. table 13 shows how the state of the bit corresponds to the mode of operation. see figure 66 for the contents of the input shift register during the internal reference setup command. table 13. reference setup command db0 action 0 internal reference off (default) 1 internal reference on x s c2 c1 c0 a2 a1 a0 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 x reserved don?t care 1 0 1 x x x x x x x x x x x x x x x x x x rst command dac address (don?t care) don?t care don?t care reset mode 06342-113 figure 64. software reset command r s c2 c1 c0 a2 a1 a0 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 x reserved don?t care 1 0 0 x x x x x x x x x x x x x pd1 pd0 x x dacb daca command dac address (don?t care) don?t care don?t care power- down mode don?t care dac select (1 = dac selected) 06342-112 figure 65. power up/down command r s c2 c1 c0 a2 a1 a0 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 x reserved don?t care 1 1 1 x x x x x x x x x x x x x x x x x x ref command dac address (don?t care) don?t care don?t care reference mode 06342-114 figure 66. reference setup command
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 27 of 32 application information using a reference as a power supply for the ad56x7r/ad56x7 because the supply current required by the ad56x7r/ad56x7 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see figure 67). this is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 v or 3 v, for example, 15 v. the voltage reference outputs a steady supply voltage for the ad56x7r/ad56x7. if the low dropout ref195 is used, it must supply 450 a of current to the ad56x7r/ad56x7 with no load on the output of the dac. when the dac output is loaded, the ref195 also needs to supply the current to the load. the total current required (with a 5 k load on the dac output) is 450 a + (5 v/5 k) = 1.45 ma the load regulation of the ref195 is typically 2 ppm/ma, resulting in a 2.9 ppm (14.5 v) error for the 1.45 ma current drawn from it. this corresponds to a 0.191 lsb error. 2-wire serial interface scl sda 5v v out = 0v to 5v v dd gnd 15 v ref195 ad5627r/ AD5647R/ ad5667r/ ad5627/ ad5667 06342-043 figure 67. ref195 as power supply to the ad56x7r/ad56x7 bipolar operation using the ad56x7r/ad56x7 the ad56x7r/ad56x7 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 68. the circuit gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achieved using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = r1 r2 v r1 r2 r1 d v v dd dd o 536 , 65 where d represents the input code in decimal (0 to 65535). with v dd = 5 v, r1 = r2 = 10 k, v 5 536 , 65 10 ? ? ? ? ? ? ? = d v o this is an output voltage range of 5 v, with 0x0000 corre- sponding to a ?5 v output, and 0xffff corresponding to a +5 v output. 2-wire serial interface r2 = 10k ? +5v ?5v ad820/ op295 ad5627r/ AD5647R/ ad5667r/ ad5627/ ad5667 v dd v out r1 = 10k ? 5v 0.1f 10f + 5 v sda scl gnd 06342-044 v o figure 68. bipolar operation with the ad56x7r/ad56x7 power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad56x7r/ad56x7 should have separate analog and digital sections, each having its own area of the board. if the ad56x7r/ad56x7 are in a system where other devices require an agnd to dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad56x7r/ad56x7. the power supply to the ad56x7r/ad56x7 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be located as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitor should be the tantalum bead type. it is important that the 0.1 f capacitor have low effective series resistance (esr) and effective series inductance (esi), for example, common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a two-layer board.
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 28 of 32 outline dimensions 3.00 bsc sq index area top view 1.50 bcs sq exposed pad (bottom view) 1.74 1.64 1.49 2.48 2.38 2.23 1 6 10 0.50 bsc 0.50 0.40 0.30 5 pin 1 indicator 0.80 0.75 0.70 0.05 max 0.02 nom s eating plane 0.30 0.23 0.18 0.20 ref 0.80 max 0.55 typ side view figure 69. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm x 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 70. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 29 of 32 ordering guide model temperature range accuracy on-chip reference max i 2 c speed package description package option branding ad5627bcpz-r2 1 ?40c to +105c 1 lsb inl none 400 khz 10-lead lfcsp_wd cp-10 -9 da1 ad5627bcpz-reel7 1 ?40c to +105c 1 lsb inl none 400 khz 10-lead lfcsp_wd cp-10-9 da1 ad5627brmz 1 ?40c to +105c 1 lsb inl none 400 khz 10-lead msop rm-10 da1 ad5627brmz-reel7 1 ?40c to +105c 1 lsb inl none 400 khz 10-lead msop rm-10 da1 ad5627rbcpz-r2 1 ?40c to +105c 1 lsb inl 1.25 v 400 khz 10-lead lfcsp_wd cp-10-9 d9j ad5627rbcpz-reel7 1 ?40c to +105c 1 lsb inl 1.25 v 400 khz 10-lead lfcsp_wd cp-10-9 d9j ad5627rbrmz-1 1 ?40c to +105c 1 lsb inl 2.5 v 400 khz 10-lead msop rm-10 da7 ad5627rbrmz-1reel7 1 ?40c to +105c 1 lsb inl 2.5 v 400 khz 10-lead msop rm-10 da7 ad5627rbrmz-2 1 ?40c to +105c 1 lsb inl 2.5 v 3.4 mhz 10-lead msop rm-10 da8 ad5627rbrmz-2reel7 1 ?40c to +105c 1 lsb inl 2.5 v 3.4 mhz 10-lead msop rm-10 da8 AD5647Rbcpz-r2 1 ?40c to +105c 4 lsb inl 1.25 v 400 khz 10-lead lfcsp_wd ru-14 d9g AD5647Rbcpz-reel7 1 ?40c to +105c 4 lsb inl 1.25 v 400 khz 10-lead lfcsp_wd ru-14 d9g AD5647Rbrmz 1 ?40c to +105c 4 lsb inl 2.5 v 400 khz 10-lead msop rm-10 d9g AD5647Rbrmz-reel7 1 ?40c to +105c 4 lsb inl 2.5 v 400 khz 10-lead msop rm-10 d9g ad5667bcpz-r2 1 ?40c to +105c 12 lsb inl none 400 khz 10-lead lfcsp_wd cp-10-9 d9z ad5667bcpz-reel7 1 ?40c to +105c 12 lsb inl none 400 khz 10-lead lfcsp_wd cp-10-9 d9z ad5667brmz 1 ?40c to +105c 12 lsb inl none 400 khz 10-lead msop rm-10 d9z ad5667brmz-reel7 1 ?40c to +105c 12 lsb inl none 400 khz 10-lead msop rm-10 d9z ad5667rbcpz-r2 1 ?40c to +105c 12 lsb inl 1.25 v 400 khz 10-lead lfcsp_wd cp-10-9 d8x ad5667rbcpz-reel7 1 ?40c to +105c 12 lsb inl 1.25 v 400 khz 10-lead lfcsp_wd cp-10-9 d8x ad5667rbrmz-1 1 ?40c to +105c 12 lsb inl 2.5 v 400 khz 10-lead msop rm-10 da5 ad5667rbrmz-1reel7 1 ?40c to +105c 12 lsb inl 2.5 v 400 khz 10-lead msop rm-10 da5 ad5667rbrmz-2 1 ?40c to +105c 12 lsb inl 2.5 v 3.4 mhz 10-lead msop rm-10 da6 ad5667rbrmz-2reel7 1 ?40c to +105c 12 lsb inl 2.5 v 3.4 mhz 10-lead msop rm-10 da6 eval-ad5667rebz 1 evaluation board 1 z = pb-free part.
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 30 of 32 notes
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 31 of 32 notes
ad5627r/AD5647R/ad5667r , ad5627/ad5667 rev. 0 | page 32 of 32 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06342-0-1/07(0)

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